This invention relates generally to semiconductor field effect transistors and fabrication processes, and more particularly the invention relates to field effect transistors having gate-drain shields to reduce capacitative coupling. The invention has particular applicability to RF/microwave power MOSFET transistors including an extended drain MOSFET, vertical DMOS transistor, and lateral DMOS transistor.
The gate to drain feedback capacitance (Cgd or Crss) of any MOSFET device must be minimized in order to maximize RF gain and minimize signal distortion. The gate to drain feedback capacitance is critical since it is effectively multiplied by the voltage gain of the device or C.sub.effective =Crss (1+gm R.sub.L) where gm is the transconductance of the device and R.sub.L is the load resistance. The gate length must be minimized also to reduce transit time, increase transconductance, and reduce the on-resistance of the device.
Sub-micron narrow gate lithography can be used to enhance the characteristics of the MOSFET device, but fabrication of such device requires the use of very expensive wafer stepper systems.
Heretofore the use of a Faraday shield made of metal or polysilicon formed over the gate structure has been proposed as disclosed in U.S. Pat. No. 5,252,848. As shown in FIG. 1, a lateral DMOS transistor including an N+ source 10, an N+ drain 12, and an N- drain extended region 14 are separated by a P channel region 16 over which is formed a gate electrode 18 separated from the channel region 16 by gate oxide 20. In accordance with the U.S. Pat. No. 5,252,848 patent, the source metal contact 22 extends over gate 18 and is isolated therefrom by an insulative layer 24. The extended source metal 22 provides a Faraday shield between the gate 18 and the drain metal 26 thus reducing gate-drain capacitance. However, substantial gate-drain capacitance exists between gate 18 and the N- drain region 14 as illustrated at 28.
Spectrian (Assignee of the present application) has introduced a buried shield LDMOS transistor as illustrated in FIG. 2 in which gate-drain shielding is enhanced by providing a buried shield 30 which underlies gate 18 to reduce the capacitance 28 of FIG. 1. Further, a buried shield metal 30 is placed on the surface of insulator 24 to reduce capacitance between gate 18 and drain metal 26. However, the overlap of gate 18 over buried shield 30 results in higher input capacitance for the device.
Thus, there is a high cost of scaling down gate dimensions to try and minimize gate-drain capacitance. The described prior art devices using Faraday shields do not completely minimize the gate-drain capacitance, and prior art structures cannot be successfully applied to vertical DMOS devices. The overlap of the gate over the shield in the structure of FIG. 2 results in a higher input capacitance.